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-- Company: 
-- Engineer: 
-- 
-- Create Date: 2022/08/03 16:43:31
-- Design Name: 
-- Module Name: MUX4_1A - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

ENTITY MUX4_1A IS
  PORT (
    A : IN STD_LOGIC;
    B : IN STD_LOGIC;
    C : IN STD_LOGIC;
    D : IN STD_LOGIC;
    S : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
    Z : OUT STD_LOGIC
  );
END MUX4_1A;

ARCHITECTURE Behavioral OF MUX4_1A IS
BEGIN
  PROCESS (S, A, B, C, D) IS
  BEGIN
    CASE S IS
      WHEN "00" => Z <= A;
      WHEN "01" => Z <= B;
      WHEN "10" => Z <= C;
      WHEN "11" => Z <= D;
      WHEN OTHERS => Z <= 'X';
    END CASE;
  END PROCESS;
END Behavioral;